-------------------------------------------------------------------------------
-- Archivo: 			         counter.vhdl
-- Fecha de creación:            25/01/2011
-- Última fecha de modificación: 28/01/2011
-- Diseñador: 			         Cesar A. Fuguet T.
-- Diseño: 			             counter
-- Propósito: 			         Contador para generar los índices de los
--                               registros a seleccionar y la operación en base
--                               al valor de la cuenta y la instrucción actual
-------------------------------------------------------------------------------

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity counter is
    port(
        CLK_i : in std_logic;
        RESET_i : in std_logic;
        COUNTER_o : out std_logic_vector(1 downto 0));

end counter;

architecture behavioral of counter is

    signal count_reg : std_logic_vector(1 downto 0);
    signal count_next : std_logic_vector(1 downto 0);
begin

    count_next <= std_logic_vector(unsigned(count_reg) + 1);

--    with count_reg select
--        count_next <= 
--            "00" when "11",
--            "01" when "00",
--            "10" when "01",
--            "11" when others;

    process(CLK_i, RESET_i, count_next)
    begin
        if (CLK_i = '1' and CLK_i'event) then
            if (RESET_i = '1') then
                count_reg <= "00";
            else
                count_reg <= count_next;
            end if;
        end if;
    end process;
 
    COUNTER_o <= count_reg;

end behavioral;

-- vim: tabstop=4 : expandtab : shiftwidth=4
